1. Field of the Invention
The present invention relates to the field of semiconductor production, and, more particularly, to an alignment structure used in the photolithographical formation of semiconductor features and/or used for metrology/defect inspection tool alignment and measurement.
2. Description of the Related Art
The manufacturing process of integrated circuits involves the fabrication of numerous semiconductor elements on a single substrate, usually referred to as a wafer, by means of a lithographic process. In microlithography, features of the semiconductor elements, such as field effect transistors, are printed on a photoresist layer that is subsequently developed to produce a photoresist pattern. This pattern is then used as a mask for a further process, for example an etch process, to produce the required feature in the material layer underlying the patterned photoresist. Currently, in modern integrated circuits, semiconductor elements are patterned having a minimum feature size of about 0.18 micrometers. Thus, the lithographic apparatus and the equipment used for transferring an image from a mask to the wafer and for patterning corresponding features must exhibit the capability of reliably and reproducibly generating feature sizes with tolerances that are defined by very strict design rules.
In addition to quality of the lithographic imagery and the processes involved in patterning circuit features, the accuracy with which an image can be positioned on the surface of the wafer is of comparable importance since a plurality of photolithographical steps have to be performed, i.e., a sequence of masking layers is required to obtain the final integrated circuit. The features patterned on successive layers must bear a spatial relationship to one another to ensure the functionality of the final device. Accordingly, each level must be precisely aligned to one or more of the previous levels. Due to unavoidable inaccuracies in the processes for transferring and patterning features, a minimum registration tolerance must be allowed between the edges of a feature of a given level with respect to a preceding level. This minimum tolerance is one of the aforementioned design rules used in laying out the circuit patterns for a specified integrated circuit. Thus, numerous metrology processes are carried out to effectively monitor the various manufacturing stages of the semiconductor device with respect to the individual process steps necessary to transfer and pattern circuit features.
The metrology systems employed for monitoring the various stages of the semiconductor device have to reliably produce accurate measurement results, thereby yielding a high throughput due to economical constraints. In most metrology systems, the wafer must be precisely aligned with respect to the metrology apparatus to obtain the required information. For instance, a defect inspection tool may be used to identify the number, the size and the accurate position of any defects generated by the manufacturing process of interest. Furthermore, many of the metrology systems are automated or semi-automated to achieve improved throughput and accuracy. For example, an automated overlay measurement system may handle 50-60 wafers per hour, thereby providing high measurement accuracy, whereas only 10-15 wafers may be manually measured per hour. Due to the automated measurement process, however, the wafers to be inspected have to be appropriately aligned in the measurement apparatus by means of a corresponding alignment mark on the wafer. Usually, step-and-repeat and step-and-scan lithography systems are used in modem integrated circuit fabrication such that a large number of exposure fields, each of which may represent the area of a final chip, are generated, while corresponding alignment marks are required in each exposure field to fully indicate each individual exposure field, in particular at a region where four exposure fields come into contact with each other.
Accordingly, a need exists for an effective alignment structure that may conveniently be used in automated metrology apparatus, such as in defect inspection tools, that clearly indicates the exposure field corner and cannot be confused with other structures in the exposure field.
In accordance with the present invention, a semiconductor device structure comprises a die region defined by an exposure field of a lithography apparatus used for fabricating the semiconductor device, wherein the die region comprises a material layer having a corner structure formed therein and located at a corner of the die region in spaced relationship to an edge of the die region. The semiconductor structure further comprises a delineation region that at least partially encloses the corner structure and that comprises a plurality of elongated patterns formed in the material layer, wherein the delineation region is asymmetric with respect to point symmetry and axial symmetry and also defines an inner region of the corner structure. Furthermore, the delineation region exhibits a plurality of angles of approximately 90xc2x0 that are defined by at least some of the elongated patterns.
Due to the unique shape of the corner structure defined by the delineation region without any point and axial symmetry, the corner structure according to the present invention is unambiguously and easily detectable in any type of apparatus using optical alignment, such as measurement apparatus for metrology and defect inspection tools. Moreover, the inner region of the corner structure may be filled with any appropriate pattern that is in agreement with the design rules for the formation of the semiconductor device, thereby allowing the identification of specific process layers and the monitoring of process quality.